Package-on-package fabrication has been widely used to increase memory bandwidth in a variety of electronics applications (e.g., Smartphone technology). Current package-on-package technology has reached an upward limit as to the number of electronic interconnects (i.e., I/O ports). Therefore, various different technologies are under development in order to meet higher I/O requirements.
One type of technology provides a 3D/TSV solution. However, TSV technology is not very mature and 3D assembly is quite challenging in order to produce fine-pitch electrical interconnects for package-on-package fabrication. Other technologies are currently being developed to form more dense electrical interconnections between packages. These technologies include (i) using wire-bond technology; (ii) HCP (high copper pillar); and (iii) Cu—SnAg plated bumps. The development of each of these technologies is suffering from various design issues that make it difficult to fabricate an increased density of electrical interconnects between packages in package-on-package electronic systems.